Semiconductor devices typically include multiple individual components formed on or within a substrate. Such devices often comprise a high density section and a low density section. For example, as illustrated in prior art FIG. 1, a memory device such as a flash memory 10 comprises one or more high density core regions 12 and a low density peripheral portion 14 on a single substrate 16. The high density core regions 12 typically consist of at least one MxN array of individually addressable, substantially identical memory cells and the low density peripheral portion 14 typically includes input/output (I/O) circuitry and circuitry for selectively addressing the individual cells (such as decoders for connecting the source, gate and drain of selected cells to predetermined voltages or impedances to effect designated operations of the cell such as programming, reading or erasing).
The memory cells within the core portion 12 are coupled together in a circuit configuration, such as that illustrated in prior art FIG. 2. Each memory cell 20 has a drain 22, a source 24 and a stacked gate 26. Each stacked gate 26 is coupled to a word line (WL.sub.0, WL.sub.1, . . . , WL.sub.N) while each drain 22 is coupled to a bit line (BL.sub.0, BL.sub.1, . . . , BL.sub.N). Lastly, each source 24 is coupled to a common source line CS. Using peripheral decoder and control circuitry, each memory cell 20 can be addressed for programming, reading or erasing functions.
Prior art FIG. 3 represents a fragmentary cross-sectional diagram of a typical memory cell 20 in the core region 12 of prior art FIGS. 1 and 2. Such a memory cell 20 typically includes the source 24, the drain 22 and a channel 28 in a substrate 30; and the stacked gate structure 26 overlying the channel 28. The stacked gate 26 includes a thin gate dielectric layer 32 (commonly referred to as the tunnel oxide) formed on the surface of the substrate 30. The tunnel oxide layer 32 coats a portion of the top surface of the silicon substrate 30 and serves to support an array of different layers directly over the channel 28. The stacked gate 26 includes a lower most or first film layer 38, such as doped polycrystalline silicon (polysilicon or poly I) layer which serves as a floating gate 38 that overlies the tunnel oxide 32. On top of the poly I layer 38 is an interpoly dielectric layer 40. The interpoly dielectric layer 40 is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer, or in the an alternative can be another dielectric layer such as tantalum pentoxide. Finally, the stacked gate 26 includes an upper or second polysilicon layer (poly II) 44 which serves as a polysilicon control gate overlying the ONO layer 40. The control gates 44 of the respective cells 20 that are formed in a given row share a common word line (WL) associated with the row of cells (see, e.g., prior art FIG. 2). In addition, as highlighted above, the drain regions 22 of the respective cells in a vertical column are connected together by a conductive bit line (BL). The channel 28 of the cell 20 conducts current between the source 24 and the drain 22 in accordance with an electric field developed in the channel 28 by the stacked gate structure 26.
According to conventional operation, the memory cell 20 (e.g., flash memory cell) operates in the following manner. The memory cell 20 is programmed by applying a relatively high voltage V.sub.G (e.g., approximately 12 volts) to the control gate 38 and a moderately high voltage V.sub.D (e.g., approximately 9 volts) to the drain 22 in order to produce "hot" (high energy) electrons in the channel 28 near the drain 22. The hot electrons accelerate across the tunnel oxide 32 and into the floating gate 34 and become trapped in the floating gate 38 because the floating gate 38 is surrounded by insulators (the interpoly dielectric 40 and the tunnel oxide 32). As a result of the trapped electrons, a threshold voltage (V.sup.T) of the memory cell 20 increases by about 3 to 5 volts. This change in the threshold voltage (and thereby the channel conductance) of the memory cell 20 created by the trapped electrons is what causes the memory cell 20 to be programmed.
To read the memory cell 20, a predetermined voltage V.sub.G that is greater than the threshold voltage of an unprogrammed memory cell, but less than the threshold voltage of a programmed memory cell, is applied to the control gate 44. If the memory cell 20 conducts, then the memory cell 20 has not been programmed (the memory cell 20 is therefore at a first logic state, e.g., a zero "0"). Conversely, if the memory cell 20 does not conduct, then the memory cell 20 has been programmed (the memory cell 20 is therefore at a second logic state, e.g., a one "1"). Thus, each memory cell 20 may be read in order to determine whether it has been programmed (and therefore identify the logic state of the memory cell 20).
In order to erase the memory cell 20, a relatively high voltage V.sub.s (e.g., approximately 12 volts) is applied to the source 24 and the control gate 44 is held at a ground potential (V.sub.G =0), while the drain 22 is allowed to float. Under these conditions, a strong electric field is developed across the tunnel oxide 32 between the floating gate 38 and the source region 24. The electrons that are trapped in the floating gate 38 flow toward and cluster at the portion of the floating gate 38 overlying the source region 24 and are extracted from the floating gate 38 and into the source region 22 by way of Fowler-Nordheim tunneling through the tunnel oxide 32. Consequently, as the electrons are removed from the floating gate 38, the memory cell 20 is erased.
Having described a structural arrangement of the memory cell 20, attention is now brought to fabrication of the memory device 10. FIG. 4 illustrates an overall arrangement of the memory device 10 at an early stage of formation. A substrate 30 is shown which comprises regions of thick oxide (field oxide) 34 and thin oxide (tunnel oxide) 32. The field oxide 34 provides for electrically insulating transistors from one and other. A poly I layer 38 has been laid down over the substrate 30, and sections of the poly I layer 38 have been patterned and masked such that an unmasked portion 42 is etched away using convention photolithographic techniques so as to form a series of poly I layer rows 38. FIG. 5 illustrates an ONO layer 40 laid down over the poly I layer rows 38 and the partially exposed field oxide regions 34 between the rows of poly I layer 38. More particularly, since sections of the poly I layer 38 have been etched away, gaps 42 exist between the rows of poly I layer 38 such that sidewalls of the poly I layer rows become coated with the ONO layer material 40 as it is being deposited. The etching step of the poly I layer 38 causes the ONO layer 40 being deposited thereon to be non-uniform in step height. More specifically, since there are gaps 42 between the rows of poly I layer 38, and since the ONO layer 40 conforms to the topography on which it is deposited, the ONO that lies along the sidewalls of the etched poly I lines is significantly thicker that the ONO on top of either the flat portion of the poly I or the flat portion of the field oxide. It is to be appreciated that the thickness of the ONO layer 40 in the figures is shown to be relatively the same as the other layers for ease of understanding, however, the ONO layer 40 is actually very thin relative to the poly I layer 38 and poly II layer 44 (FIG. 6a).
After application of the ONO layer 40, the poly II layer 44 is laid down over the ONO layer 40 as shown in FIG. 6a. Like the ONO layer 40, the poly II layer 44 also includes undulations as a result of the gaps 42 between rows of the poly I layer 38. The gaps 42 result in the poly II layer 44 being undulated such that portions of the poly II layer 44 adjacent an edge of a respective poly I layer row 38 (where the ONO layer 40 is thickest) is greater in height with respect to the substrate surface 30 than a portion of the poly II layer 44 which lies relatively over other areas. As will be discussed in greater detail below, the gaps 42 may lead to discontinuity in ONO 40 and poly II 44 thickness and even possibly film cracks or breaks.
FIG. 6b illustrates a substantially large maximum step height (y.sub.M) that results because of the undulating poly II layer 44. In particular, the step height of a portion of the poly II layer that lies respectively over a poly I layer row 38 has a step height of y.sub.1, land a portion of the poly II layer that lies respectively over the gap 42 between adjacent poly I layer rows has a step height of Y.sub.2. However, the portion of the poly II layer 44 which represents an undulation (i.e., the transition from the poly II layer lying over the poly I layer row 38 and over the gap 42 between poly I layer rows 38) has a step height of y.sub.M, where y.sub.M is substantially greater in height than y.sub.1 or Y.sub.2 and results in problems relating to overetch requirements and the formation of an ONO fence as will be discussed in greater detail below.
Referring now to FIG. 7, a resist 50 is lithographically patterned over portions of the poly II layer 44. Then, the poly II layer 44 is etched away at portions not covered by the resist 50, the etched away portion of poly II layer is generally designated at 54.
FIG. 8 is a partial cross-sectional view of the memory device 10 taken at the portion 54. As is seen, the poly II layer 44 has been etched away leaving an ONO layer 40 laid down atop and along vertical sidewalls of the poly I layer 38. The field oxide 34 and tunnel oxide 36 of the substrate 30 are not shown for ease of understanding. In FIG. 9, the ONO layer 40 is shown being substantially etched away using conventional etching techniques. The ONO layer 40 has a substantially greater step height at side wall portions 60 of the poly I layer 38. As a result, these side wall portions of ONO do not become completely etched away and leave what is coined an ONO fence 64 (FIG. 10) along the sidewalls of the poly I layer 38.
In FIG. 11, the poly I layer 38 is substantially etched away using conventional etching techniques. However, a problem often occurs at this step involving formation of poly stringers. Poly stringers result from incomplete removal of poly I from the unmasked portions of the wafer during etch. The poly stringers of concern here are created during the self-aligned etch (SAE). During the SAE, the ONO 40 and then the poly I 38 between adjacent second gate lines is etched away. In the SAE, the second gate lines act as a mask. This results in substantially perfect alignment of the first gate with the second gate along a direction perpendicular to the second gate lines-hence, the name self-aligned etch. During the SAE, the ONO 64 along the sidewalls of the poly I is only partially removed, resulting in the ONO fence. When the poly I 38 is etched, for some memory cells a small "string" of polysilicon is hidden from the etch by the ONO fence. If this happens to even a few cells in the memory the memory chip will not function properly. As shown in FIG. 12, the ONO fence 64 acts as an umbrella and shields portions of the poly I layer 38 from being etched away. These remaining portions of poly I material are known as poly I stringers 70a and 70b as shown in FIG. 13, which may result in electrically shorting adjacent memory cells 20. In other words, the poly I etching step of FIG. 11 serves in part to isolate one memory cell 20 from another. However, if a portion of the poly I layer 38 is not etched away and forms a conductive path (e.g., poly stringer 70) from one memory cell 20 to another, the memory cells 20 will become electrically shorted.
FIG. 13 illustrates in perspective view the ONO fences 64a, 64b that have lead to the formation of poly stringers 70a, 70b which may cause shorting of poly I layers 38a and 38b of two memory cells 20a and 20b, respectively. The polysilicon floating gates 38a and 38b rest on the oxide coated substrate 30. The ONO fences 64a and 64b remain along the sidewalls of the poly I layers 38a and 38b and in the region 80 between the two memory cells 20a and 20b. The additional layers that make up the stacked gate structure 26 of the respective memory cells 20a and 20b are not shown in prior art FIG. 13 for sake of simplicity.
As long as the initial etching of the polysilicon floating gate 38 (which delineates cells 20 along a single word line) occurs in an ideally anisotropic manner, no poly stringers are formed during the second etching of the floating gate 38 (which delineates separate word lines). It is well known, however, that anisotropic etch processes do not repeatably provide ideally anisotropic profiles. Instead, most anisotropic etch processes provide non-ideal profiles in the range of about 85-95.degree. (wherein 90.degree. is ideal). A non-ideal anisotropic etch profile as is illustrated in prior art FIG. 12 leaves an angled ONO fence 64 which acts as an umbrella (or shield) to the poly I etch.
More specifically, when the polysilicon gate 38 is subsequently etched (in an anisotropic manner via, e.g., reactive ion etching (RIE)), as illustrated in prior art FIG. 11, the angled ONO fence 64 shields a portion of the polysilicon gate 38, resulting in anisotropic etched polysilicon gate 38 and the resulting poly stringers 70 into their macroscopic context (as illustrated in prior art FIG. 13), it is clear that the poly stringers 70 pose a substantial reliability problem since the poly stringers 70 in the etched region 80 can short out the word lines in regions 82 and 84, respectively. That is, instead of the etched region 80 electrically isolating the word lines in regions 82 and 84 from one another, the poly stringers 70 (which are conductive) span the etched region 80 and cause the poly I layers (i.e., floating gates) 38a and 38b in the regions 82 and 84 to be shorted together.
Consequently, in light of the above, it would be desirable to have a method for fabricating a memory cell such that the formation of an ONO fence and resulting poly stringers is eliminated or otherwise substantially reduced.